Static Random Access Memory devices ("SRAMs"), Electrically Programmable Read Only Memory devices ("EPROMs"), and flash Electrically Erasable Programmable Read Only Memory devices ("flash EEPROMs") often include Address Transition Detection (ATD) circuitry that increases the speed of read operations for the memory devices. In response to detecting a transition in the value of the address lines of the memory device, the ATD circuitry typically resets the sense amplifiers and latches the data output corresponding to the previous address.
Resetting the sense amplifiers causes the sense amplifiers to be cleared or otherwise set up to sense the newly addressed portions of the memory device. For differential sense amplifiers, resetting typically entails the equalization of sense amplifiers. For single-ended sense amplifiers, resetting typically entails precharging the bitlines of the memory device. The previously sensed data is latched to prevent the output of invalid data that may occur because of the sense amplifiers fluctuating during the resetting process. Resetting the sense amplifiers and latching the previous data are operations that are typically required for every memory read operation.
There are some instances wherein it is undesirable to reset the sense amplifiers and latch the output in response to an address transition. For example, for typical prior asynchronous memory devices, if a user changes the address before the data of the immediately previous read operation are output, the ATD circuitry resets the sense amplifiers, and the data of the immediately prior read operation are never output. The outputs of the memory device remain at the value of the last validly sensed quantity of data.
Another example is when a synchronous memory device that can output some maximum number of bits is configured to output less than the maximum number of bits. For example, a memory device capable of outputting a word (sixteen bits) of data at a time may be configured to sequentially output each byte (eight bits) of the data word. Wherein the user has typically requested only a single byte of data, the memory device typically senses both bytes of the data word simultaneously, and the least significant bit of the address is used to control a multiplexer that selects the desired byte of the data word. If the sense amplifiers were reset in response to a transition of the least significant bit of the address, the sensing of the second byte of data would need to be repeated, slowing the speed of operation for the memory device. Asynchronous devices typically solve this problem by ignoring the least significant bit of the address for purposes of address transition detection.
For synchronous memory devices, the ATD circuitry may be activated in response to control signals that indicate a valid address, rather than in response to detecting an address transition. The memory device ignores the values on the address lines when the control signals indicate that the address is not valid. When sequentially reading out the bytes of a data word, the address of the second byte of data must be passed to the memory device so that the multiplexer may be appropriately configured to output the second byte of data. Therefore, the second address of the data word is indicated as a valid address, which activates the ATD circuitry to reset the sense amplifiers even though the desired data is already contained in the sense amplifiers. A mechanism should be provided to prevent the ATD circuitry from resetting the sense amplifiers and latching the output in such an instance.